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  quad spdt switch adg333a rev. a in fo rmation furn ished by an alog d e v i c e s is believed to be accurate and reliable. how e ver, n o resp on sibili ty is assume d b y a n alog de vices fo r its use, nor for an y i n fri n geme nt s of p a t e nt s or ot h e r ri ght s o f th ird parties th at may result fro m its use . specifications subjec t to chan g e witho u t n o tice. no licen s e is g r an te d by implicati o n or ot herwi s e u n der a n y p a t e nt or p a t e nt ri ghts of analog de v i ces. trademarks an d registered tra d ema r ks are the prop erty o f their respective ow ners. one technolog y way, p.o . box 9106, norwood, ma 02062-9106, u.s.a. t e l: 781. 329. 4 700 www.analog.com fax: 781. 461. 31 13 ? 2005 analog de vices, i n c. al l r i ght s r e ser v ed . features 44 v supply m a ximum ratings v ss to v dd anal og signal range low on resistance (45 ? max) low ?r on (5 ? max) low r on match (4 ? max) low power dissipation fast switching times t on < 17 5 ns t of f < 145 ns low leakage currents (5 na ma x) low charge inj e ction (10 pc max) break-before- make switchin g action applic ati o ns audio an d v i de o switching battery-powered systems test eq uipmen t communication systems func tio n a l block di agram s1a d1 s1b in1 in2 s2b d2 s2a s3a d3 s3b in3 in4 s4b d2 s4a adg333a switches shown for a logic 1 input 01212-001 fi g u r e 1 . general description the ad g333 a is a m o n o l i t h ic cmos de vic e c o m p r i sin g fo ur inde p e n d e n t l y s e le c t ab le s p dt swi t ch es. i t is de sig n e d o n an lc 2 mos p r o c ess, w h ich p r o v id es lo w p o w e r di ssi p a t ion yet achie v es a hi g h swi t chi n g sp e e d a nd a lo w o n r e sist a n c e . the o n r e sis t ance p r o f i l e is v e r y f l a t o v er t h e f u l l a n alog in p u t r a nge, e n su r i ng go o d l i ne ar i t y a n d l o w d i stor t i o n w h e n swi t c h in g a u dio sig n als. h i g h s w i t c h in g sp e e d als o mak e s t h e p a r t s u it a b l e f o r v i d e o s i g n a l s w it c h i n g . c m o s c o n s t r u c t i on e n su re s u l t r a l ow p o we r diss i p a t ion, ma k i ng t h e p a r t ide a l l y s u i t ed f o r po r t a b l e , ba t t e r y- po w e r e d i n s t r u m e n t s . w h e n t h ey a r e o n , ea c h swi t ch co n d uct s eq uall y w e ll i n bo t h d i re c t i o ns an d h a s an i n put s i g n a l r a nge t h a t e x te nd s to t h e p o w e r su p p lie s . i n t h e o f f co nd i t io n, sig n a l l e vel s u p to t h e s u p p lies a r e b l o c k e d . al l sw i t ches exhi b i t b r e ak-b e fo r e -ma k e swi t chi n g ac t i on fo r us e in m u lt i p lexer a p plic a t io n s . i n h e r e n t in t h e desig n is lo w cha r ge in j e c t product highlights 1. e x te nd e d s i g n a l r a nge. the ad g333 a is fa b r ic a t e d o n a n enhan c e d lc 2 mos p r o c es s, g i v i n g a n i n cr e a s e d sig n al ra n g e w h ich ext e n d s t o t h e su p p ly r a i l s . 2. l o w p o w e r di ssi p a t io n. 3. lo w r on . 4. sing l e -su p ply op er a t ion. f o r a p plica t ion s w h er e t h e a n al og sig n al is uni p ola r , t h e ad g333a ca n be o p era t e d f r o m a sin g le ra il p o w e r s u p p l y . the p a r t is f u l l y sp e c if ie d w i t h a sin g le 12 v supply .
adg333a rev. a | page 2 of 12 table of contents specifications ..................................................................................... 3 dual supply ................................................................................... 3 single supply ................................................................................. 4 absolute maximum ratings ............................................................ 5 esd caution .................................................................................. 5 ter mi nolo g y ...................................................................................... 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ..............................................8 test circ u its ..................................................................................... 10 application information ................................................................ 11 adg333a supply voltages ....................................................... 11 power supply sequencing ......................................................... 11 outline dimensions ....................................................................... 12 ordering guide .......................................................................... 12 revision history 3/05rev. 0 to rev. a updated format..................................................................universal changes to specifications tables .................................................... 3 updated outline dimensions ....................................................... 12 changes to ordering guide .......................................................... 12 10/95revision 0: initial version
adg333a rev. a | page 3 of 12 specifications dual supply v dd = +15 v, v ss = ?15 v, gnd = 0 v, unless otherwise noted. 1 table 1. parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range v ss to v dd v r on 20 ? typ v d = 10 v, i s = C1 ma 45 45 ? max ? r on 5 ? max v d = 5 v, i s = C10 ma r on match 4 ? max v d = 10 v, i s = C10 ma leakage currents v dd = +16.5 v, v ss = C16.5 v source off leakage i s (off) 0.1 na typ v d = 15.5 v, v s = +15.5 v 0.25 3 na max figure 15 channel on leakage i d , i s (on) 0.1 na typ v s = v d = 15.5 v 0.4 5 na max figure 16 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = 0 v or v dd 0.5 a max dynamic characteristics 2 t on 90 ns typ r l = 300 ?, c l = 35 pf; 175 ns max v s = 10 v; figure 17 t off 80 ns typ r l = 300 ?, c l = 35 pf; 145 ns max v s = 10 v; figure 17 break-before-make delay, t open 10 ns min r l = 300 ?, c l = 35 pf; v s = +5 v; figure 18 charge injection 2 pc typ v d = 0 v, r d = 0 ?, c l = 10 nf; 10 pc max v dd = +15 v, v ss = C15 v; figure 19 off isolation 72 db typ r l = 75 ?, c l = 5 pf, f = 1 mhz; v s = 2.3 v rms; figure 20 channel-to-channel crosstalk 85 db typ r l = 75 ?, c l = 5 pf, f = 1 mhz; v s = 2.3 v rms; figure 21 c s (off) 7 pf typ c d , c s (on) 26 pf typ power requirements i dd 0.05 ma typ digital inputs = 0 v or 5 v 0.25 0.35 ma max i ss 0.01 a typ 1 5 a max v dd /v ss 3/20 v min/v max |v dd | = |v ss | 1 temperature range is as follows: b version: ?40c to +85c. 2 guaranteed by design; not subject to production test.
adg333a rev. a | page 4 of 12 single supply v dd = +12 v, v ss = 0 v 10%, gnd = 0 v, unless otherwise noted. 1 table 2. parameter +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 v to v dd v ron 35 ? typ v d = 1 v, 10 v, i s = C1 ma 75 ? max leakage currents v dd = 13.2 v source off leakage i s (off) 0.1 na typ v d = 12.2 v/1 v, v s = 1 v/12.2 v 0.25 3 na max figure 15 channel on leakage i d , i s (on) 0.1 na typ v s = v d = 12.2 v/1 v 0.4 5 na max figure 16 digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 0.005 a typ v in = 0 v or v dd 0.5 a max dynamic characteristics 2 t on 110 ns typ r l = 300 ?, c l = 35 pf; 200 ns max v s = 8 v; figure 17 t off 100 ns typ r l = 300 ?, c l = 35 pf; 180 ns max v s = 8 v; figure 17 break-before-make delay, t open 10 ns min r l = 300 ?, c l = 35 pf; ns min v s = 5 v; figure 18 charge injection 5 pc typ v d = 6 v, r d = 0 w, c l = 10 nf; v dd = 12 v, v ss = 0 v; figure 19 off isolation 72 db typ r l = 75 ?, c l = 5 pf, f = 1 mhz; v s = 1.15 v rms; figure 20 channel-to-channel crosstalk 85 db typ r l = 75 ?, c l = 5 pf, f = 1 mhz; v s = 1.15 v rms; figure 21 c s (off) 12 pf typ c d , c s (on) 25 pf typ power requirements v dd = 13.5 v i dd 0.05 ma typ digital inputs = 0 v or 5 v 0.25 0.35 ma max v dd 3/30 v min/v max 1 temperature range is as follows: b version: ?40c to +85c. 2 guaranteed by design; not subject to production test.
adg333a r e v. a | pa ge 5 o f 1 2 absolute maximum ratings t a = 2 5 c u n l e s s ot he r w i s e not e d. table 3. p a r a m e t e r m i n v dd to v ss +44 v v dd to gnd C0.3 v to +30 v v ss to gnd +0.3 v to C30 v analog, digital i n puts 1 v ss C 2 v to v dd + 2 v or 20 ma, whichev e r occu rs first continuous current, s or d 20 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle max) 40 ma operating tem p erature range indus t rial (b vers io n) ?40c to +85c storage temperature range ?65c to +125c junction tempe r ature 150c ja , thermal impedance pdip package 103c/w soic package 74c/w ssop package 130c/w lead temperature, soldering (10 sec) 260c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 overvo l tage at in, s, o r d i s c l amped b y internal dio d e s . current shou ld be l imited to the maxi m um ratings given. s t r e s s es a b o v e t h os e list e d u nde r a b s o l u te m a xi m u m r a t i n g s ma y ca us e p e r m a n e n t dama ge to t h e de vi ce. t h is is a st r e ss r a t i ng on ly ; f u n c t i on a l op e r at i o n of t h e d e v i c e a t t h e s e or an y o t h e r con d i t ions a b o v e t h o s e i ndic a te d i n t h e op er a t io na l s e c t io n o f t h is sp e c if ic a t io n is no t im pl ie d . e x p o sur e t o a b s o l u te max i m u m r a t i ng co ndi t i on s fo r ex tende d p e r i o d s ma y a f fe c t de vice rel i a b i l i t y . table 4. truth table logic switch a switch b 0 off on 1 on off esd caution esd (electrostatic discharge) se nsit ive device. e l ectrostatic char ges as high as 4000 v readily accumulate on the human body and test eq uipment and can discharge without detection. although this product features proprietary esd protection circ uitry, permanen t dama ge may occur on devic e s sub j ected to high energy electrostatic di scharge s . ther efore, pro p er esd precaution s are reco mm ended to avoid performance degradation or l o ss of functiona l ity.
adg333a rev. a | page 6 of 12 terminology r on ohmic resistance between d and s. ?r on r on variation due to a change in the analog input voltage with a constant load current. r on match difference between the r on of any two channels. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v d (v s ) analog voltage on terminals d, s. c s (off) off switch source capacitance. c d (off) off switch drain capacitance. c d , c s (on) on switch capacitance. t on delay between applying the digital control input and the output switching on. t off delay between applying the digital control input and the output switching off. t open break-before-make delay when switches are configured as a multiplexer. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off switch. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching.
adg333a r e v. a | pa ge 7 o f 1 2 pin conf igurations and f u ncti on descriptions in1 1 s1a 2 d1 3 s1b 4 in4 20 s4a 19 d4 18 s4b 17 v ss 5 gnd 6 s2b 7 v dd 16 nc 15 s3b 14 d2 8 d3 13 s2a 9 s3a 12 in2 10 in3 11 nc = no connect adg333a top view (not to scale) 01212-002 in1 1 s1a 2 d1 3 s1b 4 in4 20 s4a 19 d4 18 s4b 17 v ss 5 v dd 16 gnd 6 nc 15 s2b 7 s3b 14 d2 8 d3 13 s2a 9 s3a 12 in2 10 in3 11 nc = no connect adg333a top view (not to scale) 01212-003 in1 1 s1a 2 d1 3 s1b 4 in4 20 s4a 19 d4 18 s4b 17 v ss 5 gnd 6 s2b 7 v dd 16 nc 15 s3b 14 d2 8 d3 13 s2a 9 s3a 12 in2 10 in3 11 nc = no connect adg333a top view (not to scale) 01212-004 f i gure 2. pdip p i n configur ation f i gure 3. soic p i n configur ation f i gure 4. sso p pin c o nfigur ation ta ble 5. pi n f u nct i on d e s c ri pt i o ns pin no. mnemonic description 1, 10, 11, 20 in1, in2, i n 3, in4 logic control input. 2, 4, 7, 9, 12, 14, 17, 19 s1a, s1b, s2b, s2a, s3a, s3b, s4b, s4a source terminal. can be an inpu t or output. 3, 8, 13, 18 d1, d2, d3, d4 drain terminal. can be an input or output. 5 v ss most negative p o wer supply potential in dual suppl ies. in single-supply applic ations, it can be connected to ground. 6 gnd ground (0 v ) ref e rence. 1 5 n c n o c o n n e c t . 1 6 v dd m o st positive power supply po tential.
adg333a r e v. a | pa ge 8 o f 1 2 typical perf orm ance cha r acte ristics t a = 25 c v dd = +5v v ss = ? 5v v dd = +10v v ss = ? 10v v dd = +15v v ss = ? 15v v dd , v s (v) r on ( ? ) 60 50 40 30 10 20 ? 1 5 ? 10 0 ?5 5 1 0 1 5 01212-005 fi g u r e 5 . r on a s a f u ncti on o f v d (v s ): du al s u ppl y t a = 25 c v dd = +5v v ss = ? 5v v dd = +10v v ss = ? 10v v dd = +15v v ss = ? 15v v dd , v s (v) r on ( ? ) 100 90 80 70 60 50 40 30 20 03 9 61 2 01212-006 1 5 fi g u r e 6 . r on a s a f u ncti on o f v d (v s ): single sup p l y +125 c +85 c +25 c ?4 0 c v dd = +15v v ss = ? 15v v dd , v s (v) r on ( ? ) 45 40 30 35 25 20 10 15 ? 1 5 ? 10 0 ?5 5 1 0 1 5 01212-007 fi g u r e 7 . r on a s a f u ncti on o f v d (v s ) f o r d i fferent t e mper atur es : du al s u ppl y v dd , v s (v) r on ( ? ) 60 50 40 30 10 20 0 3 6 9 12 15 01212-008 +125 c +85 c +25 c ?40 c v dd = 15v v ss = 0v fi g u r e 8 . r on a s a f u ncti on o f v d (v s ) f o r d i fferent t e mper atur es : single sup p l y i s (off) i d (on) v dd = +16.5v v ss = ? 16.5v t a = 25 c v d , v s (v) le akage curre nt (na) 0.004 0.002 ? 0.002 0 ? 0.004 ? 0.006 ? 0.010 ? 0.008 ? 1 5 ? 10 0 ?5 5 1 0 1 5 01212-009 i s (on) f i g u re 9. l e akag e current s as a f u nc t i on of v d (v s ): du al s u ppl y i s (off) i s (on) v dd = +16.5v v ss = ? 16.5v t a = 25 c v d , v s (v) le akage curre nt (na) 0.001 ? 0.001 0 ? 0.002 ? 0.004 ? 0.003 03 6 9 01212-010 1 2 i d (on) f i g u re 10. l e akag e current s as a f u nc t i on of v d (v s ): single sup p l y
adg333a r e v. a | pa ge 9 o f 1 2 c l = 10nf v dd = +12v v ss = 0v v dd = +16.5v v ss = ? 16.5v v s (v) q ( p c) 20 15 10 5 ?2 0 ?1 5 ?1 0 ?5 0 ? 1 5 ? 10 0 ?5 5 1 0 1 5 01212-011 f i g u re 11. cha r g e i n jec t i o n as a f u nc t i on of v s v d = +2v v s = ? 2v v dd (v) s w itching time (ns ) 160 140 120 100 80 60 0 5 10 20 15 01212-012 f i g u re 12. swit chi n g ti me as a f u nc t i o n of v d v dd = +16.5v v ss = ? 16.5v t a = 25 c switching frequency (khz) i dd (ma) 1 0.8 0.6 0.4 0.2 0 0 200 400 1000 600 800 01212-013 f i g u re 13. i dd as a f u nc t i o n of sw it chi n g f r equenc y
adg333a rev. a | page 10 of 12 test circuits v d i ds sd r on = v 1 /i ds v 1 01212-014 f i g u re 14. o n r e s i s t anc e v d sd i s (off) v s 01212-015 a f i g u re 15. o f f l e akag e v d sd nc nc = no co nne ct 01212-016 i d (on) a f i g u re 16. o n l e akag e d gn d in sa sb ?1 0 v +10 v v dd v dd v ss v ss v s v ou t r l 30 0 ? c l 35 p f 0. 1 f 0. 1 f 50 % 50 % 50 % 5 0% t on t of f v in v s +3v 0v + 10v 0v ? 10v 01212-017 f i gure 1 7 . s w i t chin g t i m e s d gn d in sa sb v dd v dd v ss v ss v s v ou t r l 30 0 ? c l 35 p f 0. 1 f 0. 1 f 01212-018 3v 0v v in v ou t v s 50 % 5 0% t open f i gure 18. break-b e fore -mak e d e l a y , t op e n v dd v dd v ss v ss v ou t in c l 10 n f gn d v in v ou t q inj = c l ? v out ? v out 3v 0v 0v ds a v d r d 01212-019 f i gure 1 9 . char ge i n jectio n v ss v ou t gn d sd v in v s 01212-020 v dd v dd v ss 0. 1 f 0. 1 f r l 75 ? v ss gn d sd v in 1 v s 01212-021 v dd v dd v ss 0. 1 f 0. 1 f v ou t nc cha nne l - t o - c han ne l cro s s t al k 20 lo g | v s /v ou t | v in 2 75 ? r l 75 ? sd fi g u r e 2 0 . o f f i s o l a t i o n fi g u r e 21. channe l-to - c hann el crosstalk
adg333a rev. a | page 11 of 12 application information adg333a supply voltages the adg333a can operate from a dual or signal supply. v ss should be connected to gnd when operating with a single supply. when using a dual supply, the adg333a can also operate with unbalanced supplies; for example v dd = 20 v and v ss = ?5 v. the only restrictions are that v dd to gnd must not exceed 30 v, v ss to gnd must not drop below ?30 v, and v dd to v ss must not exceed +44 v. it is important to remember that the adg333a supply voltage directly affects the input signal range, the switch on resistance and the switching times of the part. the effects of the power supplies on these characteristics can be clearly seen from the typical performance characteristics curves. power supply sequencing when using cmos devices, care must be taken to ensure correct power-supply sequencing. incorrect power-supply sequencing can result in the device being subjected to stresses beyond those listed in the absolute maximum ratings. this is also true for the adg333a. always turn on v dd first, followed by v ss and the logic signals. an external signal within the maxi- mum specified ratings can then be safely presented to the source or drain of the switch
adg333a rev. a | page 12 of 12 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001-ad 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 20 1 10 11 0.100 (2.54) bsc 1.060 (26.92) 1.030 (26.16) 0.980 (24.89) pin 1 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) f i gure 22. 20-l ead p l astic d u al in-lin e p a ck age [ p dip ] nar r o w b o dy (n- 2 0) di me nsio ns sho w n i n i n che s a n d ( m il lim e t e r s) controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards ms-013ac 0.75 (0.0295) 0.25 (0.0098) 20 11 10 1 8 0 45 1.27 (0.0500) 0.40 (0.0157) seating plane 0.30 (0.0118) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 2.65 (0.1043) 2.35 (0.0925) 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) bsc 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 13.00 (0.5118) 12.60 (0.4961) coplanarity 0.10 f i gure 23. 20-l ead standar d s m all o u tline p a ck age [s oi c ] w i de body (r - 2 0) di me nsio ns sho w n i n mi ll im e t e r s a n d (i nc he s) 20 11 10 1 7. 50 7. 20 6. 90 8. 20 7. 80 7. 40 5. 60 5. 30 5. 00 co p l a nari t y 0. 10 0.05 min 1.85 1.75 1. 65 0.65 bsc 0.25 0.09 0.95 0.75 0.55 8 4 0 2.00 max 0.38 0.22 sea t i n g p l ane pin 1 compliant to jedec standards mo-150ae f i gure 24. 2 0 -l ead shrink sm al l o u t lin e p a ckage [s sop ] (r s-20) di me nsio ns sho w n i n mi ll im e t e r s ordering guide model temperature r a nge package descri ption package option adg333abn ?40c to +85c 20-lead pl astic dual in-line package (pdip) n-20 adg333abr ?40c to +85c 20-lead stan dard small outline package (soic) r-20 adg333abr-re el ?40c to +85c 20-lead st andard small outline package (soic) r-20 adg333abrz 1 ?40c to +85c 20-lead standard small outline package (soic) r-20 adg333abrz-reel 1 ?40c to +85c 20-lead standard small outline package (soic) r-20 adg333abrs ?40c to +85c 20-lead shri nk small outline package (ssop) rs-20 adg333abrs-r eel ?40c to +85c 20-lead sh rink small outline package (ssop) rs-20 adg333abrsz 1 ?40c to +85c 20-lead shrink sm all outline package (ssop) rs-20 adg333abrsz- reel 1 ?40c to +85c 20-lead shrink sm all outline package (ssop) rs-20 1 z = pb-free part. ? 2005 analog d e vices, inc. a ll rights reserve d . tra d ema r ks and registered trade m arks are th e proper ty of their respective owne rs. c01212C0 C 3/05(a)


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